Memory provides data storage for electronic systems. Flash memory is one type of memory, and has numerous uses in modern computers and devices. For instance, modern personal computers may have BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features.
NAND may be a basic architecture of flash memory, and may be configured to comprise vertically-stacked memory cells.
Before describing NAND specifically, it may be helpful to more generally describe the relationship of a memory array within an integrated arrangement. FIG. 1 shows a block diagram of a prior art device 100 which includes a memory array 102 having a plurality of memory cells 103 arranged in rows and columns along with access lines 104 (e.g., wordlines to conduct signals WL0 through WLm) and first data lines 106 (e.g., bitlines to conduct signals BL0 through BLn). Access lines 104 and first data lines 106 may be used to transfer information to and from the memory cells 103. A row decoder 107 and a column decoder 108 decode address signals A0 through AX on address lines 109 to determine which ones of the memory cells 103 are to be accessed. A sense amplifier circuit 115 operates to determine the values of information read from the memory cells 103. An I/O circuit 117 transfers values of information between the memory array 102 and input/output (I/O) lines 105. Signals DQ0 through DQN on the I/O lines 105 can represent values of information read from or to be written into the memory cells 103. Other devices can communicate with the device 100 through the I/O lines 105, the address lines 109, or the control lines 120. Memory control unit 118 controls memory operations performed on the memory cells 103 utilizing signals on the control lines 120. The device 100 can receive supply voltage signals Vcc and Vss on a first supply line 130 and a second supply line 132, respectively. The device 100 includes a select circuit 140 and an input/output (I/O) circuit 117. The select circuit 140 can respond, via the I/O circuit 117, to signals CSEL1 through CSELn to select signals on the first data lines 106 and the second data lines 113 that can represent the values of information to be read from or to be programmed into the memory cells 103. The column decoder 108 can selectively activate the CSEL1 through CSELn signals based on the A0 through AX address signals on the address lines 109. The select circuit 140 can select the signals on the first data lines 106 and the second data lines 113 to provide communication between the memory array 102 and the I/O circuit 117 during read and programming operations.
The memory array 102 of FIG. 1 may be a NAND memory array, and FIG. 2 shows a block diagram of a three-dimensional NAND memory device 200 which may be utilized for the memory array 102 of FIG. 1. The device 200 comprises a plurality of strings of charge-storage devices. In a first direction (Z-Z′), each string of charge-storage devices may comprise, for example, thirty-two charge-storage devices stacked over one another with each charge-storage device corresponding to one of, for example, thirty-two tiers (e.g., Tier0-Tier31). The charge-storage devices of a respective string may share a common channel region, such as one formed in a respective pillar of semiconductor material (e.g., polysilicon) about which the string of charge-storage devices is formed. In a second direction (X-X′), each first group of, for example, sixteen first groups of the plurality of strings may comprise, for example, eight strings sharing a plurality (e.g., thirty-two) of access lines (i.e., “global control gate (CG) lines”, also known as wordlines, WLs). Each of the access lines may couple the charge-storage devices within a tier. The charge-storage devices coupled by the same access line (and thus corresponding to the same tier) may be logically grouped into, for example, two pages, such as P0/P32, P1/P33, P2/P34 and so on, when each charge-storage device comprises a cell capable of storing two bits of information. In a third direction (Y-Y′), each second group of, for example, eight second groups of the plurality of strings, may comprise sixteen strings coupled by a corresponding one of eight data lines. The size of a memory block may comprise 1,024 pages and total about 16 MB (e.g., 16 WLs×32 tiers×2 bits=1,024 pages/block, block size=1,024 pages×16 KB/page=16 MB). The number of the strings, tiers, access lines, data lines, first groups, second groups and/or pages may be greater or smaller than those shown in FIG. 2.
FIG. 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of FIG. 2 in an X-X′ direction, including fifteen strings of charge-storage devices in one of the sixteen first groups of strings described with respect to FIG. 2. The plurality of strings of the memory block 300 may be grouped into a plurality of subsets 310, 320, 330 (e.g., tile columns), such as tile columnI, tile columnj and tile columnK, with each subset (e.g., tile column) comprising a “partial block” of the memory block 300. A global drain-side select gate (SGD) line 340 may be coupled to the SGDs of the plurality of strings. For example, the global SGD line 340 may be coupled to a plurality (e.g., three) of sub-SGD lines 342, 344, 346 with each sub-SGD line corresponding to a respective subset (e.g., tile column), via a corresponding one of a plurality (e.g., three) of sub-SGD drivers 332, 334, 336. Each of the sub-SGD drivers 332, 334, 336 may concurrently couple or cut off the SGDs of the strings of a corresponding partial block (e.g., tile column) independently of those of other partial blocks. A global source-side select gate (SGS) line 360 may be coupled to the SGSs of the plurality of strings. For example, the global SGS line 360 may be coupled to a plurality of sub-SGS lines 362, 364, 366 with each sub-SGS line corresponding to the respective subset (e.g., tile column), via a corresponding one of a plurality of sub-SGS drivers 322, 324, 326. Each of the sub-SGS drivers 322, 324, 326 may concurrently couple or cut off the SGSs of the strings of a corresponding partial block (e.g., tile column) independently of those of other partial blocks. A global access line (e.g., a global CG line) 350 may couple the charge-storage devices corresponding to the respective tier of each of the plurality of strings. Each global CG line (e.g., the global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a corresponding one of a plurality of sub-string drivers 312, 314 and 316. Each of the sub-string drivers may concurrently couple or cut off the charge-storage devices corresponding to the respective partial block and/or tier independently of those of other partial blocks and/or other tiers. The charge-storage devices corresponding to the respective subset (e.g., partial block) and the respective tier may comprise a “partial tier” (e.g., a single “tile”) of charge-storage devices. The strings corresponding to the respective subset (e.g., partial block) may be coupled to a corresponding one of sub-sources 372, 374 and 376 (e.g., “tile source”) with each sub-source being coupled to a respective power source.
The NAND memory device 200 is alternatively described with reference to a schematic illustration of FIG. 4.
The memory array 200 includes wordlines 2021 to 202N, and bitlines 2281 to 228M.
The memory array 200 also includes NAND strings 2061 to 206M. Each NAND string includes charge-storage transistors 2081 to 208N. The charge-storage transistors may use floating gate material (e.g., polysilicon) to store charge, or may use charge-trapping material (such as, for example, silicon nitride, metallic nanodots, etc.) to store charge.
The charge-storage transistors 208 are located at intersections of wordlines 202 and strings 206. The charge-storage transistors 208 represent non-volatile memory cells for storage of data. The charge-storage transistors 208 of each NAND string 206 are connected in series source-to-drain between a source-select device (e.g., source-side select gate, SGS) 210 and a drain-select device (e.g., drain-side select gate, SGD) 212. Each source-select device 210 is located at an intersection of a string 206 and a source-select line 214, while each drain-select device 212 is located at an intersection of a string 206 and a drain-select line 215. The select devices 210 and 212 may be any suitable access devices, and are generically illustrated with boxes in FIG. 1.
A source of each source-select device 210 is connected to a common source line 216. The drain of each source-select device 210 is connected to the source of the first charge-storage transistor 208 of the corresponding NAND string 206. For example, the drain of source-select device 2101 is connected to the source of charge-storage transistor 2081 of the corresponding NAND string 2061. The source-select devices 210 are connected to source-select line 214.
The drain of each drain-select device 212 is connected to a bitline (i.e., digit line) 228 at a drain contact. For example, the drain of drain-select device 2121 is connected to the bitline 2281. The source of each drain-select device 212 is connected to the drain of the last charge-storage transistor 208 of the corresponding NAND string 206. For example, the source of drain-select device 2121 is connected to the drain of charge-storage transistor 208N of the corresponding NAND string 2061.
The charge-storage transistors 208 include a source 230, a drain 232, a charge-storage region 234, and a control gate 236. The charge-storage transistors 208 have their control gates 236 coupled to a wordline 202. A column of the charge-storage transistors 208 are those transistors within a NAND string 206 coupled to a given bitline 228. A row of the charge-storage transistors 208 are those transistors commonly coupled to a given wordline 202.
Three-dimensional integrated memory assemblies (e.g., three-dimensional NAND) may have vertical channel pillars extending to horizontal wiring (e.g., source lines). It can be difficult to achieve uniform contact between the channel pillars and the associated horizontal wiring. It would be desirable to develop improved methods for fabricating integrated memory assemblies such that desired contact between the channel material pillars and the horizontal wiring is achieved.